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2-45 features ? 256 x 256 channel non-blocking switch ? programmable frame integrity for wideband channels ? automatic identi?cation of st-bus/gci interface backplanes ? per channel tristate control ? patented message mode ? non-multiplexed microprocessor interface ? single +5 volt supply ? available in dip-40, plcc-44 and qfp-44 packages ? pin compatible with mt8980 device applications ? medium size digital switch matrices ? hyperchannel switching (e.g., isdn h0) ? st-bus/mvip ? interface functions ? serial bus control and monitoring ? centralized voice processing systems ? data multiplexer description the mt8985 enhanced digital switch device is an upgraded version of the popular mt8980d digital switch (dx). it is pin compatible with the mt8980d and retains all of the mt8980d's functionality. this vlsi device is designed for switching pcm-encoded voice or data, under microprocessor control, in digital exchanges, pbxs and any st-bus/mvip environment. it provides simultaneous connections for up to 256 64kb/s channels. each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. as the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. the constant throughput delay feature allows grouped channels such as isdn h0 to be switched through the device maintaining its sequence integrity. the mt8985 is ideal for medium sized mixed voice/data switch and voice processing applications. figure 1 - functional block diagram sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 serial to parallel converter data memory frame counter control register control interface output mux connection memory parallel to serial converter cs r/ w a5/ a0 dta d7/ d0 csto c4i f0i v dd v ss ode sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 ds issue 5 march 1997 mt8985 enhanced digital switch cmos st-bus ? family ordering information MT8985AE 40 pin plastic dip mt8985ap 44 pin plcc mt8985al 44 pin qfp -40 c to +85 c
mt8985 2-46 figure 2 - pin connections pin description pin # name description 40 dip 44 plcc 44 qfp 1240 dt a data acknowledgement (open drain output). this active low output indicates that a data bus transfer is complete. a pull-up resistor is required at this output. 2-9 3-5 7-11 41-43 1-5 sti0- sti7 st-bus input 0 to 7 (inputs). serial data input streams. these streams have 32 channels at data rates of 2.048 mbit/s. 10 12 6 v dd +5 volt power supply rail. 11 13 7 f0i frame pulse (input): this input accepts and automatically identi?es frame synchronization signals formatted according to different backplane speci?cations such as st-bus and gci. 12 14 8 c4i clock (input). 4.096 mhz serial clock for shifting data in and out of the data streams. 13-18 15-17 19-21 9-11 13-15 a0-a5 address 0 to 5 (inputs). these lines provide the address to mt8985 internal registers. 19 22 16 ds data strobe (input). this is the input for the active high data strobe on the microprocessor interface. this input operates with cs to enable the internal read and write generation. 20 23 17 r/ w read/write (input). this input controls the direction of the data bus lines (d0-d7) during a microprocessor access. dta sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 a3 a4 a5 ds csto ode sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 d5 d6 d7 cs 1 6 5 4 3 2 4443424140 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 nc sti1 dta ode sto1 nc sti2 sti0 csto sto0 sto2 nc a4 ds cs d6 nc a3 a5 r/ w d7 40 pin plastic dip 44 pin plcc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 r/ w 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d5 39 44 43 42 41 40 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 17 12 13 14 15 16 18 19 20 21 22 11 23 44 pin qfp sti3 sti4 sti5 sti6 sti7 vdd f0i c4i a0 a1 a2 nc a4 ds cs d6 nc a3 a5 r/ w d7 d5 sto3 sto4 sto5 sto6 sto7 vss d0 d1 d2 d3 d4 nc sti1 dta ode sto1 nc sti2 sti0 csto sto0 sto2
mt8985 2-47 21 24 18 cs chip select (input). active low input enabling a microprocessor read or write of control register or internal memories. 22-29 25-27 29-33 19-21 23-27 d7-d0 data bus 7 to 0 (bidirectional). these pins provide microprocessor access to data in the internal control register, connect memory high, connect memory low and data memory. 30 34 28 v ss ground rail. 31-38 35-39 41-43 29-33 35-37 sto7- sto0 st-bus outputs 7 to 0 (three-state outputs). serial data output streams. these streams are composed of 32 channels at data rates of 2.048 mbit/s. 39 44 38 ode output drive enable (input). this is an output enable for the sto0 to sto7 serial outputs. if this input is low sto0-7 are high impedance. if this input is high each channel may still be put into high impedance by software control. 40 1 39 csto control st-bus output (output). this output is a 2.048 mb/s line which contains 256 bits per frame. the level of each bit is controlled by the contents of the csto bit in the connect memory high locations. 6, 18, 28, 40 12,22 34, 44 nc no connection. pin description pin # name description 40 dip 44 plcc 44 qfp functional description with the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at n x 64 kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. the mt8985 device provides both functions and allows existing systems based on the mt8980d to be easily upgraded to maintain the data integrity while multiple channel data are transported. the device is designed to switch 64 kbit/s pcm or n x 64 kbit/s data. the mt8985 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. by using mitel message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the mitel mt8972, isdn transceivers and t1/ cept trunk interfaces through the st-bus interface. different digital backplanes can be accepted by the mt8985 device without user's intervention. the mt8985 device provides an internal circuit that automatically identi?es the polarity and format of frame synchronization input signals compatible to st-bus and gci interfaces. de vice operation a functional block diagram of the mt8985 device is shown in figure 1. the serial st-bus streams operate continuously at 2.048 mb/s and are arranged in 125 m s wide frames each containing 32 8-bit channels. eight input (sti0-7) and eight output (sto0-7) serial streams are provided in the mt8985 device allowing a complete 256 x 256 channel non- blocking switch matrix to be constructed. the serial interface clock for the device is 4.096 mhz, as required in st-bus and gci speci?cations. data memory the received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position data memory. the sequential addressing of the data memory is generated by an internal counter that is reset by the input 8 khz frame pulse ( f0i) mar king the frame boundaries of the incoming serial data streams. depending on the type of information to be switched, the mt8985 device can be programmed to perform
mt8985 2-48 time slot interchange functions with different throughput delay capabilities on a per-channel basis. for voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. in multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch. data to be output on the serial streams may come from two sources: data memory or connect memory. locations in the connect memory, which is split into high and low parts, are associated with particular st-bus output streams. when a channel is due to be transmitted on an st-bus output, the data for the channel can either be switched from an st-bus input (connection mode) or it can be originated from the microprocessor (message mode). if a channel is con?gured in connection mode, the source of the output data is the data memory. if a channel is con?gured in message mode, the source of the output data is the connect memory low. data destined for a particular channel on the serial output stream is read from the data or connect memory low during the previous channel time slot. this allows enough time for memory access and internal parallel to serial conversion. connection and message modes in connection mode, the addresses of input source for all output channels are stored in the connect memory low. the connect memory low locations are mapped to each location corresponding to an output 64 kb/s channel. the contents of the data memory at the selected address are then transferred to the parallel to serial converters. by having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. in message mode the cpu writes data to the connect memory low locations which correspond to the output link and channel number. the contents of the connect memory low are transferred to the parallel to serial converter one channel before it is to be output. the connect memory low data is transmitted each frame to the output until it is changed by the cpu. the per-channel functions available in the mt8985 are controlled by the connect memory high bits, which determine whether individual output channels are selected into speci?c conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. in addition, the connect memory high provides one bit to allow the user to control the state of the csto output pin. if an output channel is set to three-state condition, the tdm serial stream output will be placed in high impedance during that channel time. in addition to the per-channel three-state control, all channels on the tdm outputs can be placed in high impedance at one time by pulling the ode input pin in low. this overrides the individual per-channel programming on the connect memory high bits. the connect memory data is received via the microprocessor interface at d0-d7 lines. the addressing of the mt8985 internal registers, data and connect memories is performed through address input pins and some bits of the device's control register. the higher order address bits come from the control register, which may be written or read through the microprocessor interface. the lower order address bits come directly from the external address line inputs. for details on the device addressing, see software control and control register description. serial interface timing the mt8985 master clock ( c4i) is a 4.096 mhz allowing serial data link con?guration at 2.048 mb/s to be implemented. the mt8985 frame synchronization pulse can be formatted according to st-bus or gci interface speci?cations; i.e., the frame pulse can be active in high (gci) or low (st-bus). the mt8985 device automatically detects the presence of an input frame pulse and identi?es the type of backplane present on the serial interface. upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. in st-bus mode, every second falling edge of the 4.096 mhz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. in gci mode, every second rising edge of the 4.096 mhz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. dela y thr ough the mt8985 the transfer of information from the input serial streams to the output serial streams results in a delay through the mt8985 device. the delay through the mt8985 device varies according to the mode selected in the v/c bit of the connect memory high.
mt8985 2-49 variable delay mode the delay in this mode is dependent only on the combination of source and destination channels and it is not dependent on the input and output streams. the minimum delay achievable in the mt8985 device is 3 time slots. in the mt8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). the same occurs if the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the information is input. the information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. any switching con?guration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. table 1 shows the possible delays for the mt8985 device in variable delay mode: table 1 constant delay mode in this mode frame integrity is maintained in all switching con?gurations by making use of a multiple data-memory buffer technique where input channels written in any of the buffers during frame n will be read out during frame n+2. in the mt8985, the minimum throughput delay achiev-able in constant delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). likewise, the maximum delay is achieved when the ?rst time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay. to summarize, any input time slot from input frame n will be always switched to the destination time slot on input channel output channel throughput delay n m=n, n+1 or n+2 m-n + 32 timeslots n m>n+2 m-n time slots n m mt8985 2-50 figure 4 - control register bits x = dont care bit name description 7 sm split memory. when 1, all subsequent reads are from the data memory and writes are to the connection memory low, except when the control register is accessed again. the memory select bits need to be set to specify the memory for the operations. when 0, the memory select bits specify the memory for subsequent operations. in either case, the stream address bits select the subsection of the memory which is made available. 6 me message enable. when 1, the contents of the connection memory low are output on the serial output streams except when in high impedance. when 0, the connection memory bits for each channel determine what is output. 4-3 ms1-ms0 memory select bits. the memory select bits operate as follows: 0-0 - not to be used 0-1 - data memory (read only from the cpu) 1-0 - connection memory low 1-1 - connection memory high 2-0 sta2-0 stream address bits 2-0. the number expressed in binary notation on these bits refers to the input or output st-bus stream which corresponds to the subsection of memory made accessible for subsequent operations. sm me x ms1 ms0 sta2 sta1 sta0 76543210 low, then the mt8985 internal control register is addressed (see figure 3). if a5 input line is high, then the remaining address input lines are used to select memory subsections of 32 locations corresponding to the number of channels per input or output stream. as explained in the control register description, the address input lines and the stream address bits (sta) of the control register give the user the capability of selecting all positions of the mt8985 data and connect memories. the data in the control register consists of split memory and message mode bits, memory select and stream address bits (see figure 4). the memory select bits allow the connect memory high or low or the data memory to be chosen, and the stream address bits de?ne an internal memory subsections corresponding to input or output st-bus streams. bit 7 (split memory) of the control register allows split memory operation whereby reads are from the data memory and writes are to the connect memory low. the message enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the connect memory low (cml) are output on the st-bus output streams once every frame unless the ode input pin is low. if me bit is high, then the mt8985 behaves as if bits 2 (message channel) and 0 (output enable) of every connect memory high (cmh) locations were set to high, regardless of the actual value. if me bit is low, then bit 2 and 0 of each connect memory high location operates normally. in this case, if bit 2 of the cmh is high, the associated st-bus output channel is in message mode. if bit 2 of the cmh is low, then the contents of the cml de?ne the source information (stream and channel) of the time slot that is to be switched to an output. if the ode input pin is low, then all serial outputs are high-impedance. if ode is high, then bit 0 (output enable) of the cmh location enables (if high) or disables (if low) the output drivers for the corresponding individual st-bus output stream and channel. the contents of bit 1 (csto) of each connection memory high location (see figure 5) is output on csto pin once every frame. the csto pin is a 2048 mbit/s output which carries 256 bits. if csto bit is set high, the corresponding bit on csto output is
mt8985 2-51 figure 5 - connection memory high bits x = dont care figure 6 - connection memory low bits bit name description 6 v/c variable/constant throughput delay mode. this bit is used to select between variable (low) and constant delay (high) modes on a per-channel basis. 2 mc message channel. when 1, the contents of the corresponding location in connection memory low are output on the corresponding channel and stream. when 0, the contents of the programmed location in connection memory low act as an address for the data memory and so determine the source of the connection to the locations channel and stream. 1 csto csto bit. this bit drives a bit time on the csto output pin. 0 oe output enable. this bit enables the output drivers on a per-channel basis. this allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. a high enables the driver and a low disables it. bit name description 7-5 sab2-0* source stream address bits. these three bits are used to select eight source streams for the connection. bit 7 of each word is the most signi?cant bit. 4-0* cab4-0* source channel address bits 0-4. these ?ve bits are used to select 32 different source channels for the connection (the st-bus stream where the channel is present is de?ned by bits sab2-0). bit 4 is the most signi?cant bit. * if bit 2 of the corresponding connection high location is 1 or if bit 6 of the control register is 1, then these entire 8 bits are output on the channel and stream associated with this location. otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. x v/c x x x mc csto oe 76543210 sab2 sab1 sab0 cab4 cab3 cab2 cab1 cab0 76543210 transmitted in high. if csto bit is low, the corresponding bit on the csto output is transmitted in low. the contents of the 256 csto bits of the cmh are transmitted sequentially on to the csto output pin and are synchronous to the st-bus streams. to allow for delay in any external control circuitry the contents of the csto bit is output one channel before the corresponding channel on the st- bus streams. for example, the contents of csto bit in position 0 (st0, ch0) of the cmh, is transmitted synchronously with st-bus channel 31, bit 7. the contents of csto bit in position 32 (st1, ch0) of the cmh is transmitted during st-bus channel 31 bit 6. bit v/c (variable/constant delay) on the connect memory high locations allow per-channel selection between variable and constant throughput delay capabilities. initialization of the mt8985 on initialization or power up, the contents of the connection memory high can be in any state. this is a potentially hazardous condition when multiple mt8985 st-bus outputs are tied together to form matrices, as these outputs may con?ict. the ode pin should be held low on power up to keep all outputs in the high impedance condition.
mt8985 2-52 figure 7 - typical exchange, pbx or multiplexer con?guration s/u basic rate line card mt8930/31 mt8910 mt8972 st-bus to other lines layers 2 & 3 entity mt8940/ mt8941 routing matrix mt8985s mh89760/ mh89790 mt8920 m c st-bus st-bus t1/e1 link to other lines primary rate card c p u during the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. care should be taken that no two connected st-bus outputs drive the bus simultaneously. when this process is complete, the microprocessor controlling the matrices can bring the ode signal high to relinquish high impedance state control to the cmh b 0s. applications typical exchange, pbx or multiplexer figure 7 shows a typical implementation of line cards being interconnected through a central routing matrix that can scale up in channel capacity to accommodate different number of ports depending on the application. in a con?guration where the switched services utilize concatenated or grouped time slots to carry voice, data and video (channels of 128, 256 kb/s, isdn h0 and others), the central routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. figure 7 shows an example where the mt8985 device guarantees data integrity when data ?ows from the t1/e1 to the s/u interface links and vice-versa. modern technologies available today such as frame relay network using dedicated fractional t1 are one of the key applications for the mt8985 device. low latency isochronous network in today's local working group environment, there is an increasing demand for solutions on interconnection of desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable network allowing the deployment of multimedia services. existing multimedia applications require a network with
mt8985 2-53 figure 8a - private isochronous network access to public network analog connections ? ? ? ? ? ? isdn desktops n x 64 connections (e.g. video) isochronous network server 1 server 2 server 3 server 4 t1 t1 e1 ? ? ? ? ? ? ? ? ? ? ? ? t1/e1 (2b+d) predictable data transfer delays that can be implemented at a reasonable cost. the low latency isochronous network is one of the alternatives that system designers have chosen to accommodate this requirement (see figure 8a). this network can be implemented using existing tdm transmission media devices such as isdn basic (s or u) and primary rates trunks (t1 and cept) to transport mixed voice and data signals in grouped time slots; for example, 2b channels in case of isdn s or u interfaces or up to 32 channels in case of a cept link. figure 8b shows a more detailed con?guration whereby several pcs are connected to form an isochronous network. several services can be interconnected within a single pc chassis through the standardized multi vendor integration protocol (mvip). such an interface allows the distribution and interconnection of services like voice mail, integrated voice response, voice recognition, lan gateways, key systems, fax servers, video cards, etc. the information being exchanged between cards through the mvip interface on every computer as well as between computers through t1 or cept links is, in general, of mixed type where 64kb/s and n*64kb/s channels are grouped together. when such a mixed type of data is transferred between cards within one chassis or from one computer to another, the sequence integrity of the concatenated channels has to be maintained. the mt8985 device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see figure 9). this allows 8 pairs of st-bus streams to be dedicated to the mvip side whereas the remaining 8 pairs are used for local ancilliary functions in typical dual t1/e1 interface applications (figure 10). another application of the mt8985 in an mvip environment is to build an isdn s-interface card (figure 11). in this card, 7 pairs of st-bus streams are connected to the mvip interface while the remaining pair is reserved for the interconnection of mitel mt8930 (snic), mt8992 (h-phone) and the mvip interface.
mt8985 2-54 figure 8b - implementation of an isochronous network using mitel components server 1 mh89760b mh89790b st-bus mt8985s (x4) mt8930b mt8930b ? ? ? ? ? ? ? ? ? ? ? ? mvip bus isdn s-interface local t1/e1 link mvip bus server 3 (256 port switch module) server 3 mh89760b/790b mh89760b/790b mh89760b/790b st-bus mt8985s (x4) hdlc mt8985 mt8985 mt8985 mt8985 st-bus mh89760b mh89790b dual t1/e1 card mh89760b mh89790b mt8972b or analog mt8985s (x4) server 2 mvip bus st-bus to video, data, fax services local environment network access ? ? ? ? ? ? local t1/e1 link t1 e1 to video, data, fax and other services public
mt8985 2-55 figure 9 - 512-channel switch array figure 10 - dual t1/e1 card functional block diagram 8 input streams from mvip 8 input on-board st-bus streams 8 output streams to mvip 8 output on-board st-bus streams mvip direction mvip enable mt8985 #1 csto mt8985 #2 csto mt8985 #3 mt8985 #4 fdl hdlc mt8952b t1/e1 mh89760b or mh89790b hdlc mt8952b analog d-phone mt8992/93 switch mt8985 switch mt8985 switch mt8985 switch mt8985 dpll mt8941 pc interface mvip header mvip sto0-7 mvip sti0-7 fdl hdlc mt8952b t1/e1 mh89760b or mh89790b hdlc mt8952b 512 channel switch matrix
mt8985 2-56 figure 11 - s-access card functional block diagram mvip header switch matrix s interface hdlc digital phone dpll dtmf receiver pc interface hdlc sti7-1 sto7-1 sti0 sto0 mt8930b mt8941 mt8992/93 mt8870 mvip sti1-7 mvip sto1-7 mt8985
mt8985 2-57 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 12 - output test load absolute maximum ratings* parameter symbol min max units 1v dd - v ss -0.3 7 v 2 voltage on digital inputs v i v ss -0.3 v dd +0.3 v 3 voltage on digital outputs v o v ss -0.3 v dd +0.3 v 4 current at digital outputs i o 40 ma 5 storage temperature t s -65 +150 c 6 package power dissipation p d 2w recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 25 +85 c 2 positive supply v dd 4.75 5.0 5.25 v 3 input voltage v i 0v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 i n p u t s supply current i dd 10 15 ma outputs unloaded 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage (input pins) input leakage (i/o pins) i il 34 5 100 m av i between v ss and v dd 5 input pin capacitance c i 8pf 6 o u t p u t s output high voltage v oh 2.4 v i oh = 10 ma 7 output high current i oh 10 15 ma sourcing. v oh =2.4v 8 output low voltage v ol 0.4 v i ol = 5 ma 9 output low current i ol 5 10 ma sinking. v ol = 0.4v 10 high impedance leakage i oz 5 m av o between v ss and v dd 11 output pin capacitance c o 8pf output pin test point c l v ss s1 r l v dd s2 v ss s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v dd or v ss when testing output levels or high impedance states.
mt8985 2-58 ? timing is over recommended temperature & power supply voltages (v dd =5v 5%, v ss =0v, t a =C40 to 85 c). ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 13 - st-bus timing ac electrical characteristics ? - st-bus timing voltages are with respect to ground (vss) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 frame pulse width t f0iw 244 ns 2 frame pulse setup time t f0is 10 190 ns 3 frame pulse hold time t f0ih 20 190 ns 4 sto delay active to active t daa 45 100 ns c l =150 pf 5 sti setup time t stis 20 ns 6 sti hold time t stih 20 ns 7 clock period t c4i 200 244 300 ns 8 ck input low t cl 85 122 150 ns 9 ck input high t ch 85 122 150 ns 10 clock rise/fall time t r, t f 10 ns 2.0v 0.8v sti 2.0v 0.8v 2.0v 0.8v sto 2.0v 0.8v f0i t f0iw t c4i t ch t cl t f0is t daa t stis t stih t f0ih ch. 31 bit 0 ch. 0 bit 7 ch. 0 bit 6 ch. 31 bit 0 ch. 0 bit 7 ch. 0 bit 6 ch. 0 bit 5 ch. 0 bit 5 c4i t f t r
mt8985 2-59 ? timing is over recommended temperature & power supply voltages (v dd =5v 5%, v ss =0v, t a =C40 to 85 c). ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 14 - gci timing ac electrical characteristics ? - gci timing voltages are with respect to ground (vss) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 clock period t c4i 150 244 300 ns 2 pulse width t cl , t ch 73 122 150 ns 3 frame width high t wfh 244 ns 4 frame setup t f0is 10 190 ns 5 frame hold t f0ih 20 190 ns 6 data delay/clock active to active t daa 45 100 ns c l =150 pf 7 serial input setup t stis 20 ns 8 serial input hold t stih 20 ns 9 clock rise/fall time t r, t f 10 ns 2.0v 0.8v sto 2.0v 0.8v c4i 2.0v 0.8v f0i c4i f0i sti/ sto bit 0 bit 1 bit 2 bit 3 see detail a detail a note: bit 0 identifies the first bit of the gci frame t cl t ch t c4i t daa t wfh t f0is t f0ih t stis t stih 2.0v 0.8v sti t f t r
mt8985 2-60 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - serial streams for st-bus and gci backplanes characteristics sym min typ ? max units test conditions 1 o u t p u t s sto0/7 delay - active to high z t saz 100 ns r l =1 k w * , c l =150 pf 2 sto0/7 delay - high z to active t sza 100 ns c l =150 pf 3 output driver enable delay t oed 65 ns r l =1 k w * , c l =150 pf 4 csto output delay t xcd 060nsc l =150 pf figure 15 - serial outputs and external control c4i 2.0v 0.8v sto0 to sto7 2.4v 0.4v sto0 to sto7 2.4v 0.4v csto 2.4v 0.4v bit cell boundary (gci) (st-bus) * t saz t sza t xcd * figure 16 - output driver enable ode sto0 to sto7 2.0v 0.8v 2.4v 0.4v t oed * * t oed
mt8985 2-61 ? timing is over recommended temperature & power supply voltages . ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 17 - motorola non-multiplexed bus timing ac electrical characteristics ? - microprocessor bus voltages are with respect to ground (vss) unless otherwise stated . characteristics sym min typ ? max units test conditions 1 cs setup from ds rising t css 0ns 2r/ w setup from ds rising t rws 30 ns 3 add setup from ds rising t ads 5ns 4 cs hold after ds falling t csh 0ns 5r/ w hold after ds falling t rwh 5ns 6 add hold after ds falling t adh 5ns 7 data setup from dt a low on read t ddr 10 ns c l =150 pf 8 data hold on read t dhr 10 50 90 ns r l =1 k w * , c l =150 pf 9 data setup on write (fast write) t dsw 20 ns 10 valid data delay on write (slow write) t swd 122 ns 11 data hold on write t dhw 8ns 12 acknowledgement delay: reading data memory reading/writing conn. memory writing to control register reading control register t akd 560 300/370 47 70 1220 730/800 95 155 ns ns ns ns c l =150 pf 13 acknowledgement hold time t akh 10 60 110 ns r l =1 k w * , c l =150 pf cs r/ w a0-a6 d0-d7 read d0-d7 write dta t css t rws t ads t csh t rwh t adh t swd t dsw t dhr valid data t ddr t dhw t akh t akd valid data 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v ds
mt8985 2-62 notes :

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